FIGS. 5(a)-5(e) are cross-sectional views illustrating a process for producing a monolithic microwave integrated circuit (MMIC). In the process, a number of MMICs are simultaneously prepared and are separated or isolated from each other by etching through an active layer that is initially common to all of the MMICs.
As shown in FIG. 5(a), a gallium arsenide substrate 1 has disposed on it or as part of it an active layer 5. The active layer 5 is formed by epitaxially growing gallium arsenide on the substrate 1 or by ion implantation of the substrate 1. A photoresist film 3 is disposed on part of the active layer 5 where a field effect transistor (FET) is to be formed.
As shown in FIG. 5(b), using the photoresist film 3 as a mask, the substrate 1 and the active layer 5 are etched, electrically separating a portion of the active layer 5 from other similar regions on the common substrate 1. In the etching step, a three-dimensional feature, a forward mesa structure with side walls 2a and 2b, is formed. The forward mesa side walls 2a and 2b diverge in the direction of the substrate 1 from the active layer 5 and converge in the direction of the active layer 5 from the substrate 1.
The photoresist film 3 is removed and, as shown in FIG. 5(c), source electrodes 6a-6c and drain electrodes 7a and 7b, all ohmic electrodes, are deposited on the active layer 5. The source electrodes 6a and 6c extend along the respective side walls 2a and 2b and reach the substrate 1. After the formation of the source and drain electrodes, a photoresist film 8 is deposited over the electrodes, the active layer 5, and the substrate 1.
The photoresist film 8 is patterned by conventional photolithographic techniques to define locations of gate electrodes between respective source and drain electrodes. As shown in FIG. 5(d), recesses 10 are opened at each of the patterned locations in the photoresist film and extend into the active layer 5. The recesses 10 in the active layer 5 are formed by wet etching, for example, by using tartaric acid.
In the final steps of the process, illustrated in FIG. 5(e), the metal employed for the gate electrodes is vapor-deposited on the photoresist film and in the respective recesses 10 to form gate electrodes 9. The excess metal that is deposited on the photoresist film 8 is removed by a lift-off step in which the photoresist film is dissolved.
FIG. 5(c) illustrates the thickness variation in the photoresist film 8, even on the mesa side walls 2a and 2b, that is a result of the non-planar structure. It is well known that there is a relationship between the width 1, as defined in FIG. 6(b), of an aperture photolithographically formed in a photoresist pattern and the thickness h, as defined in FIG. 6(b), of the resist. As shown in FIG. 6(a), the aperture width 1 varies significantly with the resist thickness h because of the wavelength of light used to pattern the photoresist. Therefore, variations in the film thickness, as in the photoresist film 8 of FIG. 5(c), cause wide variations in the gate pattern sizes, i.e., the widths of the recesses 10 of FIG. 5(d). As a result, the recesses 10 frequently fail to meet specifications as do the FETs incorporating gate electrodes 9.
FIGS. 7(a)-7(g) illustrate a prior art method of producing a semiconductor device that is disclosed in Japanese Published Patent Application 58-53842. In that method, an attempt is made to flatten the region in which an FET, other semiconductor device element, or another element is made in order to overcome the problems illustrated in FIGS. 5(a)-5(e), 6(a), and 6(b).
In FIG. 7(a), a silicon substrate 31 has a thermal oxide film 32 grown on it and patterned with a photoresist film 33 and conventional photolithographic techniques.
As shown in FIG. 7(b), a photoresist film 33 is used as an etching mask and the substrate 31 is etched so that a three-dimensional feature is produced by reducing the substrate 31 in thickness beyond the oxide film 32. Boron ions for preventing field inversion are implanted in the silicon substrate using the resist film 33 as a mask to produce an ion implantation layer 34. As illustrated in FIG. 7(c), a silicon dioxide film 35 is deposited on the structure using a plasma chemical vapor deposition (CVD) method at a temperature below 350.degree. C. The silicon dioxide film 35 is etched, as shown in FIG. 7(d), leaving a portion 36 on the photoresist film 33 and other discontinuous portions on the ion implanted layer 34. The silicon dioxide portion 36 is removed by dissolving the underlying photoresist film 33, i.e., by a lift-off step, to produce the structure shown in FIG. 7(e).
Another silicon oxide film 37 is then deposited on the structure to fill the voids 38a of the silicon dioxide film portions on the ion implanted layer 34. However, the shape of the voids 38a is generally replicated on the surface of the film 37 so that an additional film 39 for flattening the surface of the structure is deposited on the silicon oxide film 37. The film 39 has the same etching speed as that of film 37.
By exploiting that common etching speed of films 39 and 37, the films 39 and 37 are commonly etched to expose the portion of the silicon substrate 31 that was initially covered by the oxide film 32, as shown in FIG. 7(g). That substantially planar surface is then employed to produce a semiconductor device or semiconductor device element. Since no step, i.e., non-planar or three-dimensional feature, is present where the silicon substrate 31 is exposed, a photoresist film of uniform thickness can be easily deposited and dimensional errors or variations in the completed structures avoided. However, in order to produce the relatively planar surface, it is necessary to deposit the silicon oxide film 35 at a relatively high temperature, i.e., about 350.degree. C., to cover the entire surface of the structure adequately. The elevated temperature thermally damages the resist film 33 so that it is difficult to lift-off the oxide portion 36. In addition, in order to carry out the lift-off process, it is only necessary to remove part of the silicon oxide film 35. However, in the etching of that continuous film, the voids 38a are formed. In order to provide a relatively planar surface for subsequent processing, those voids must be removed by depositing additional insulating films, such as films 37 and 39, followed by further etching. These additional steps complicate processing and increase its cost.